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GS880Z18/32/36BT-xxxV
100-Pin TQFP Commercial Temp Industrial Temp Features
* NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs * 1.8 V or 2.5 V +10%/-10% core power supply * 1.8 V or 2.5 V I/O supply * User-configurable Pipeline and Flow Through mode * LBO pin for Linear or Interleave Burst mode * Pin compatible with 2M, 4M, and 18M devices * Byte write operation (9-bit Bytes) * 3 chip enable signals for easy depth expansion * ZZ Pin for automatic power-down * JEDEC-standard 100-lead TQFP package * RoHS-compliant 100-lead TQFP package available
9Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz-150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O
rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/32/36BT-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS880Z18/32/36BT-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 100-pin TQFP package.
Functional Description
The GS880Z18/32/36BT-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power
Paramter Synopsis
-250 -200
3.0 5.0 170 195 6.5 6.5 140 160
-150
3.8 6.7 140 160 7.5 7.5 128 145
Unit
ns ns mA mA ns ns mA mA
Pipeline 3-1-1-1
tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36)
3.0 4.0 200 230 5.5 5.5 160 185
Flow Through 2-1-1-1
Rev: 1.03 6/2006
1/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
GS880Z18BT-xxxV 100-Pin TQFP Pinout (Package T)
VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV NC A A A
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
Rev: 1.03 6/2006
LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 2/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
GS880Z32BT-xxxV 100-Pin TQFP Pinout (Package T)
NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV NC A A A
NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC
Rev: 1.03 6/2006
LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 3/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
GS880Z36BT-xxxV 100-Pin TQFP Pinout (Package T)
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV NC A A A
DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA
Rev: 1.03 6/2006
LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 4/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
100-Pin TQFP Pin Descriptions Symbol
A0, A1 A CK BA BB BC BD W E1 E2 E3 G ADV CKE NC DQA DQB DQ DQD ZZ FT LBO VDD VSS VDDQ
Type
In In In In In In In In In In In In In In -- I/O I/O I/O I/O In In In In In In
Description
Burst Address Inputs; Preload the burst counter Address Inputs Clock Input Signal Byte Write signal for data inputs DQA1-DQA9; active low Byte Write signal for data inputs DQB1-DQB9; active low Byte Write signal for data inputs DQC1-DQC9; active low Byte Write signal for data inputs DQD1-DQD9; active low Write Enable; active low Chip Enable; active low Chip Enable; Active High. For self decoded depth expansion Chip Enable; Active Low. For self decoded depth expansion Output Enable; active low Advance/Load; Burst address counter control pin Clock Input Buffer Enable; active low No Connect Byte A Data Input and Output pins Byte B Data Input and Output pins Byte C Data Input and Output pins Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply
Rev: 1.03 6/2006
5/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
GS880Z18/32/36BT-xxxV NBT SRAM Functional Block Diagram
DQa-DQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst Counter
K
Register 2
SA1' SA0'
Read, Write and
Data Coherency
D
K
K
Control Logic
SA1 SA0
K
Write Address
Register 1
Match
Q
A0-An
BC
LBO
BD
W
BA
BB
K
FT
E1
E2
E3
ADV
CK
Rev: 1.03 6/2006
6/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CKE
G
Write Drivers
Memory Array
Register 2
K
Sense Amps
K
GS880Z18/32/36BT-xxxV
Functional Details
Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function Read Write Byte "a" Write Byte "b" Write Byte "c" Write Byte "d" Write all Bytes Write Abort/NOP W H L L L L L L BA X L H H H L H BB X H L H H L H BC X H H L H L H BD X H H H L L H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 1.03 6/2006
7/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
R B R B W B B D D D D D External Next External Next External Next Next None None None None None None Current L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X L-H L L L L L L L L L L L L X H L H L H L H H L L L L H X X H X H X L X X X X X L X X X X X X X L L H X X X H X X X L X L X L X X H X X L X X X H X H X H X X X X L H X X X L X L X L X X X H X L X X X L L H H X X X X X X X X X X L L L L L L L L L L L L H L
DQ
Q Q High-Z High-Z D D
Notes
1,10 2 1,2,10 3 1,3,10
High-Z 1,2,3,10 High-Z High-Z High-Z High-Z High-Z High-Z 4 1 1
Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03 6/2006
8/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Pipeline and Flow Through Read Write Control State Diagram
D
B
Deselect
R
W
D
D W R
R
New Read
B
New Write
W B
R
W
R
W
B
Burst Read
D
Burst Write
D
B
Key
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B and D represent input command codes ,as indicated in the Synchronous Truth Table. n+2 n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 1.03 6/2006
9/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Pipeline Mode Data I/O State Diagram
Intermediate
BW High Z (Data In) D
R
Intermediate W Intermediate Intermediate
RB Data Out (Q Valid) D
Intermediate
W
R
High Z B D
Intermediate
Key
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n)
Transition Next State (n+2)
Intermediate State (N+1)
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n
n+1
n+2
n+3
Clock (CK)
Command
Current State
Intermediate State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 6/2006
10/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Flow Through Mode Data I/O State Diagram
BW High Z (Data In) D
R W
RB Data Out (Q Valid) D
W
R
High Z B D
Key
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B and D represent input command codes as indicated in the Truth Tables.
n+2
n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03 6/2006
11/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 6/2006
12/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH tKC CK tZZR tZZS ZZ tZZH tKL
Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Pin 66, a No Connect (NC) on GSI's GS880Z18B/36 NBT SRAM, the Parity Error open drain output on GSI's GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor's NBT compatible SRAMs. Specifically, it is marked VDD or VDDQ on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafeTM parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI's ByteSafe NBT SRAMs (GS881Z18/36B), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open drain Parity Error output driver at Pin 66 on GSI's TQFP ByteSafe RAMs.
Rev: 1.03 6/2006
13/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage on VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V mA mA W
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version) Parameter
1.8 V Supply Voltage 2.5 V Supply Voltage 1.8 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage
Symbol
VDD1 VDD2 VDDQ1 VDDQ2
Min.
1.7 2.3 1.7 2.3
Typ.
1.8 2.5 1.8 2.5
Max.
2.0 2.7 VDD VDD
Unit
V V V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.03 6/2006
14/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
VDDQ2 & VDDQ1 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage
Symbol
VIH VIL
Min.
0.6*VDD -0.3
Typ.
-- --
Max.
VDD + 0.3 0.3*VDD
Unit
V V
Notes
1 1
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKC VDD + 2.0 V
VSS 50% VSS - 2.0 V 20% tKC
50% VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Rev: 1.03 6/2006
15/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 VDDQ/2
* Distributed Test Jig Capacitance
Figure 1
Output Load 1 DQ 50 30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) FT, ZZ Input Current Output Leakage Current
Symbol
IIL IIN IOL
Test Conditions
VIN = 0 to VDD VDD VIN 0 V Output Disable, VOUT = 0 to VDD
Min
-1 uA -100 uA -1 uA
Max
1 uA 100 uA 1 uA
DC Output Characteristics (1.8 V/2.5 V Version) Parameter
1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage 2.5 V Output Low Voltage
Symbol
VOH1 VOH2 VOL1 VOL2
Test Conditions
IOH = -4 mA, VDDQ = 1.6 V IOH = -8 mA, VDDQ = 2.375 V IOL = 4 mA IOL = 8 mA
Min
VDDQ - 0.4 V 1.7 V -- --
Max
-- -- 0.4 V 0.4 V
Rev: 1.03 6/2006
16/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Operating Currents
-250 Parameter Test Conditions Mode Symbol 0 to 70C
200 30 160 25 185 15 145 15 40 40 85 60
-200 -40 to 85C
220 30 180 25 205 15 165 15 50 50 90 65
-150 Unit
0 -40 0 -40 to 70C to 85C to 70C to 85C
170 25 140 20 155 15 130 10 40 40 75 50 190 25 160 20 175 15 150 10 50 50 80 55 140 20 130 15 130 10 120 8 40 40 60 50 160 20 150 15 150 10 140 8 50 50 65 55
Pipeline (x32/x36) Operating Current Device Selected; All other inputs VIH or VIL Output open (x18) Flow Through Standby Current Deselect Current ZZ VDD - 0.2 V Device Deselected; All other inputs VIH or VIL Pipeline Flow Through Pipeline -- Flow Through Flow Through Pipeline
IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB ISB IDD IDD
mA mA mA mA mA mA mA mA
--
Notes: 1. IDD and IDDQ apply to any combination of VDD1, VDD2, VDDQ1, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
Rev: 1.03 6/2006
17/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
AC Electrical Characteristics
Parameter
Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery
Symbol
tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
1
-250
Min 4.0 -- 1.5 1.5 1.2 0.2 5.5 -- 2.0 2.0 1.5 0.5 1.3 1.7 1.5 -- 0 -- 5 1 20 Max -- 3.0 -- -- -- -- -- 5.5 -- -- -- -- -- -- 2.5 2.5 -- 2.5 -- -- -- Min 5.0 -- 1.5 1.5 1.4 0.4 6.5 -- 2.0 2.0 1.5 0.5 1.3 1.7 1.5 -- 0 -- 5 1 20
-200
Max -- 3.0 -- -- -- -- -- 6.5 -- -- -- -- -- -- 3.0 3.0 -- 3.0 -- -- -- Min 6.7 -- 1.5 1.5 1.5 0.5 7.5 -- 2.0 2.0 1.5 0.5 1.5 1.7 1.5 -- 0 -- 5 1 20
-150
Max -- 3.8 -- -- -- -- -- 7.5 -- -- -- -- -- -- 3.0 3.8 -- 3.8 -- -- --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Pipeline
Flow Through
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.03 6/2006
18/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Pipeline Mode Timing (NBT)
Write A Read B Suspend tKH tKL Read C tKC Write D writeno-op Read E Deselect
CK
tH tS
A
A tH tS
B
C
D
E
CKE
tH tS
E*
tH tS
ADV
tH tS
W
tH tS tS tH
Bn
tH tS tLZ tKQ Q(B) Q(C) D(D) Q(E) tHZ tKQX
DQ
D(A)
Rev: 1.03 6/2006
19/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Flow Through Mode Timing (NBT)
Write A Write B Write B+1 tKL tKH
CK
Read C tKC
Cont
Read D
Write E
Read F
Write G
tH tS
CKE
tH tS
E
tH tS
ADV
tH tS
W
tH tS
Bn
tH tS
A0-An A B C D E F G
tKQ tH tS
DQ D(A) D(B)
tKQ tLZ
D(B+1) Q(C)
tKQX tHZ
Q(D)
tLZ
D(E) Q(F)
tKQX
D(G)
tOLZ tOE tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.03 6/2006
20/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
TQFP Package Drawing (Package T) L Symbol
A1 A2 b c D D1 E E1 e L L1 Y
c Pin 1
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- 0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 -- 0.75 -- 0.10
L1
e b
D D1
A1
Y
A2
E1 E
0
--
7
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
Rev: 1.03 6/2006
21/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Ordering Information--GSI NBT Synchronous SRAM Org
512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36 256K x 36 512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36 256K x 36 512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 36
Part Number1
GS880Z18BT-250V GS880Z18BT-200V GS880Z18BT-150V GS880Z32BT-250V GS880Z32BT-200V GS880Z32BT-150V GS880Z36BT-250V GS880Z36BT-200V GS880Z36BT-150V GS880Z18BT-250IV GS880Z18BT-200IV GS880Z18BT-150IV GS880Z32BT-250IV GS880Z32BT-200IV GS880Z32BT-150IV GS880Z36BT-250IV GS880Z36BT-200IV GS880Z36BT-150IV GS880Z18BGT-250V GS880Z18BGT-200V GS880Z18BGT-150V GS880Z32BGT-250V GS880Z32BGT-200V GS880Z32BGT-150V GS880Z36BGT-250V
Type
NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT
Voltage Option
1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP
Speed2 (MHz/ns)
250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5
TA3
C C C C C C C C C I I I I I I I I I C C C C C C C
Status4
MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP PQ PQ PQ PQ PQ PQ PQ
256K x 36 GS880Z36BGT-200V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: Gs880Z18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. MP = Mass Production. PQ = Pre-Qualification. 5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 6/2006
22/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
Ordering Information--GSI NBT Synchronous SRAM Org
256K x 36 512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36
Part Number1
GS880Z36BGT-150V GS880Z18BGT-250IV GS880Z18BGT-200IV GS880Z18BGT-150IV GS880Z32BGT-250IV GS880Z32BGT-200IV GS880Z32BGT-150IV GS880Z36BGT-250IV GS880Z36BGT-200IV
Type
NBT NBT NBT NBT NBT NBT NBT NBT NBT
Voltage Option
1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V
Package
RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP
Speed2 (MHz/ns)
150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5
TA3
C I I I I I I I I
Status4
PQ PQ PQ PQ PQ PQ PQ PQ PQ
256K x 36 GS880Z36BGT-150IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: Gs880Z18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. MP = Mass Production. PQ = Pre-Qualification. 5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 6/2006
23/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880Z18/32/36BT-xxxV
9Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old; New 880ZVxxB_r1 Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet
880ZVxxB_r1; 880ZVxxB_r1_01 880ZVxxB_r1_01; 880ZVxxB_r1_02 880ZVxxB_r1_02; 880ZxxB_V_r1_03
Content/Format Content Content
* Added Pb-free information for TQFP * 150 MHz speed bin removed * Updated entire document to reflect new part nomenclature
Rev: 1.03 6/2006
24/24
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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